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IS93C46D
1-KBIT SERIAL ELECTRICALLY ERASABLE PROM
FEATURES
* Industry-standard Microwire Interface -- Non-volatile data storage -- Wide voltage operation: Vcc = 1.8V to 5.5V -- Full TTL compatible inputs and outputs -- Auto increment for efficient data dump * User Configured Memory Organization -- By 16-bit or by 8-bit * Hardware and software write protection -- Defaults to write-disabled state at power-up -- Software instructions for write-enable/disable * Enhanced low voltage CMOS E2PROM technology * Versatile, easy-to-use Interface -- Self-timed programming cycle -- Automatic erase-before-write -- Programming status indicator -- Word and chip erasable -- Chip select enables power savings * Durable and reliable -- 40-year data retention after 1M write cycles -- 1 million write cycles -- Unlimited read cycles -- Schmitt-trigger inputs * Lead-free available
PRELIMINARY INFORMATION JANUARY 2007 DESCRIPTION
The IS93C46D is a 1Kb non-volatile, ISSI (R) serial EEPROM. It is fabricated using an enhanced CMOS design and process. The IS93C46D contains power-efficient read/write memory, and organization of 128 bytes of 8 bits or 64 words of 16 bits. When the ORG pin is connected to Vcc or left unconnected, x16 is selected; when it is connected to ground, x8 is selected. An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. A selected x8 byte or x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the two instructions WRITE ALL or ERASE ALL can program the entire array. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/ BUSY status by raising chip select (CS). The selftimed write cycle includes an automatic erasebefore-write capability. The device can output any number of consecutive bytes/words using a single READ instruction.
FUNCTIONAL BLOCK DIAGRAM
DUMMY BIT R/W AMPS INSTRUCTION DECODE, CONTROL, AND CLOCK GENERATION ADDRESS REGISTER ADDRESS DECODER EEPROM ARRAY 128x8 64x16
DATA REGISTER DIN INSTRUCTION REGISTER
DOUT
CS
SK
WRITE ENABLE
HIGH VOLTAGE GENERATOR
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00G 01/15/07
1
IS93C46D
PIN CONFIGURATIONS
8-Pin DIP 8-Pin JEDEC SOIC "GR" 8-pad DFN
CS 1
CS SK DIN DOUT 1 2 3 4 8 7 6 5 VCC NC ORG GND CS SK DIN DOUT 1 2 3 4 8 7 6 5 VCC NC ORG GND
8 VCC 7 NC 6 ORG 5 GND
SK 2 DIN 3 DOUT 4
(Top View)
PIN DESCRIPTIONS
CS SK DIN DOUT ORG NC Vcc GND Chip Select Serial Data Clock Serial Data Input Serial Data Output Organization Select Not Connected Power Ground
instruction begins with a start bit of the logical "1" or HIGH. Following this are the opcode (2 bits), address field (6 or 7 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clockspeed flexibility. Upon completion of bus communication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway.
Read (READ)
The READ instruction is the only instruction that outputs serial data on the DOUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical "0" bit precedes the actual 8 or 16-bit output data string.) The output on DOUT changes during the low-to-high transitions of SK (see Figure 3).
Applications
The IS93C46D is very popular in many applications which require low-power, low-density storage. Applications using this device include industrial controls, networking, and numerous other consumer electronics.
Low Voltage Read
The IS93C46D has been designed to ensure that data read operations are reliable in low voltage environments. They provide accurate operation with Vcc as low as 1.8V.
Endurance and Data Retention
The IS93C46D is designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). It provides 40 years of secure data retention without power after the execution of 1M programming cycles.
Auto Increment Read Operations
In the interest of memory transfer operation applications, the IS93C46D has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 8 or 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is brought LOW. This allows for single instruction data dumps to be executed with a minimum of firmware overhead.
Device Operations
The IS93C46D is controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each
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IS93C46D
Write Enable (WEN)
The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL, ERASE, and ERAL) can be done. When Vcc is applied, this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.)
Write All (WRALL)
The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 200 ns (tCS), the DOUT pin indicates the READY/BUSY status of the chip (see Figure 6). Vcc is required to be above 4.5V for WRALL to function properly.
Write Disable (WDS)
The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation.
Write (WRITE)
The WRITE instruction includes 8 or 16 bits of data to be written into the specified register. After the last data bit has been applied to DIN, and before the next rising edge of SK, CS must be brought LOW. If the device is write-enabled, then the falling edge of CS initiates the self-timed programming cycle (see WEN). If CS is brought HIGH, after a minimum wait of 200 ns (5V operation) after the falling edge of CS (tCS) DOUT will indicate the READY/BUSY status of the chip. Logical "0" means programming is still in progress; logical "1" means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle, tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag.
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of tCS, will cause DOUT to indicate the READ/BUSY status of the chip: a logical "0" indicates programming is still in progress; a logical "1" indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical "1" (see Figure 9). Vcc is required to be above 4.5V for ERAL to function properly.
INSTRUCTION SET - IS93C46D (1Kb)
8-bit Organization (ORG = GND) Address (1) Input Data (A6-A0) 11xxxxx (A6-A0) 01xxxxx 00xxxxx (A6-A0) 10xxxxx -- -- (D7-D0) (D7-D0) -- -- -- 16-bit Organization (ORG = Vcc) Address (1) Input Data (A5-A0) 11xxxx (A5-A0) 01xxxx 00xxxx (A5-A0) 10xxxx -- -- (D15-D0) (D15-D0) -- -- --
Instruction(2) READ WEN (Write Enable) WRITE
Start Bit 1 1 1 1 1 1 1
OP Code 10 00 01 00 00 11 00
WRALL (Write All Registers) WDS (Write Disable) ERASE ERAL (Erase All Registers)
Notes: 1. x = Don't care bit. 2. If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored, and WRITE, WRALL, ERASE, ERAL are also ignored, and READ, WEN, WDS are accepted.
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3
IS93C46D
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to +6.5 -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 5 Unit V V C C mA
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Industrial Automotive Ambient Temperature -40C to +85C -40C to +125C
o
VCC 1.8V to 5.5V 2.5V to 5.5V
Note: ISSI offers Industrial grade for Commercial applications (0 C to +70oC)
CAPACITANCE
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 5 Unit pF pF
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IS93C46D
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C for Industrial and -40C to +125C for Automotive. Symbol VOL2 VOL1 VOH2 VOH1 VIH VIL ILI ILO
Notes: Automotive grade devices in this table are tested with Vcc = 2.5V to 5.5V and 4.5V to 5.5V. An operation with Vcc <2.5V is not specified.
Parameter Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage
Test Conditions IOL = 100 A IOL = 2.1mA IOH = -100 A IOH = -400 A
Vcc 1.8V to 2.7V 2.7V to 5.5V 1.8V to 2.7V 2.7V to 5.5V 1.8V to 2.7V 2.7V to 5.5V 1.8V to 2.7V 2.7V to 5.5V
Min. -- -- VCC - 0.2 2.4 0.7XVCC 2.0 -0.3 -0.3 0 0
Max. 0.2 0.4 -- -- VCC+1 VCC+1 0.2XVCC 0.8 2.5 2.5
Unit V V V V V V A A
VIN = 0V to VCC (CS, SK,DIN,ORG) VOUT = 0V to VCC, CS = 0V
POWER SUPPLY CHARACTERISTICS
TA = -40C to +85C for Industrial, -40C to +125C for Automotive. Symbol ICC1 Parameter Vcc Read Supply Current Test Conditions CS = VIH, SK = 1 MHz, CMOS input levels CS = VIH, SK = 2 MHz, CMOS input levels CS = VIH, SK = 2 MHz, CMOS input levels CS = VIH, SK = 1 MHz, CMOS input levels CS = VIH, SK = 2 MHz, CMOS input levels CS = VIH, SK = 2 MHz, CMOS input levels CS = GND, SK = GND ORG = Vcc or Floating (x16) DIN = Vcc or GND CS = GND, SK = GND ORG = GND (x8) DIN = Vcc or GND Vcc 1.8V 2.5V 5.0V 1.8V 2.5V 5.0V 1.8V 2.5V 5.0V 1.8V 2.5V 5.0V Min. Typ. Max. -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.2 0.5 0.5 1 2 0.1 0.1 0.2 6 6 10 1 1 2 1 2 3 1 2 4 10 10 15 Unit mA mA mA mA mA mA A A A A A A
ICC2
Vcc Write Supply Current
ISB1
Standby Current
ISB2
Standby Current
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IS93C46D
AC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C for Industrial Symbol Parameter Test Conditions 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V Relative to SK 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 1.8V Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V Min. 0 0 0 250 200 200 250 200 100 250 200 200 200 100 50 100 50 50 0 0 0 50 50 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 1 2 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 400 200 100 400 200 100 400 200 200 100 100 100 10 5 5 Unit Mhz Mhz Mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tWP
SK Clock Frequency
SK HIGH Time
SK LOW Time
Minimum CS LOW Time
CS Setup Time
Din Setup Time
Relative to SK
CS Hold Time
Relative to SK
Din Hold Time
Relative to SK
Output Delay to "1"
AC Test
Output Delay to "0"
AC Test
CS to Status Valid
AC Test
CS to Dout in 3-state
AC Test, CS=VIL
Write Cycle Time
Notes:
1. C L = 100pF
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IS93C46D
AC ELECTRICAL CHARACTERISTICS
TA = -40C to +125C for Automotive Symbol Parameter Test Conditions Min. Max. Unit
fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tWP
SK Clock Frequency SK HIGH Time SK LOW Time Minimum CS LOW Time CS Setup Time Din Setup Time CS Hold Time Din Hold Time Output Delay to "1" Output Delay to "0" CS to Status Valid CS to Dout in 3-state Write Cycle Time Relative to SK Relative to SK Relative to SK Relative to SK AC Test AC Test AC Test AC Test, CS=VIL
2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V
0 0 200 200 200 100 200 200 100 50 50 50 0 0 50 50 -- -- -- -- -- -- -- -- -- --
2 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 100 200 100 200 200 100 100 5 5
Mhz Mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
Notes: 1. C L = 100pF
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IS93C46D
AC WAVEFORMS FIGURE 2. SYNCHRONOUS DATA TIMING
CS tCSS SK tDIS DIN tPD0 DOUT (READ) tSV DOUT (WRITE) (WRALL) (ERASE) (ERAL) tDIH tSKH
T tSKL tCSH
tPD1
tDF
tDF STATUS VALID
FIGURE 3. READ CYCLE TIMING
tCS CS
DIN
1
1
0
An
A0
DOUT
0
Dm
D0
*
*Address Pointer Cycles to the Next Register
Notes: To determine address bits An-A0 and data bits Dm-Do, see Instruction Set for the specific device.
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Rev. 00G 01/15/07
IS93C46D
AC WAVEFORMS FIGURE 4. WRITE ENABLE (WEN) CYCLE TIMING
tCS CS
DIN
1
0
0
1
1
DOUT = 3-state
FIGURE 5.
WRITE (WRITE) CYCLE TIMING
tCS CS
DIN
1
0
1
An
A0
Dm
D0
tSV
tDF
READY
DOUT
BUSY
tWP
Notes: 1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 2. To determine address bits An-A0 and data bits Dm-D0, see Instruction Set for the specific device.
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IS93C46D
AC WAVEFORMS FIGURE 6. WRITE ALL (WRALL) CYCLE TIMING
tCS CS
1 0 0 0 1 Dm D0
DIN
tSV
DOUT
BUSY
READY
tWP
Notes: 1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 2. To determine data bits Dm-D0, see Instruction Set for the appropriate device.
FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING
tCS CS
DIN
1
0
0
0
0
DOUT = 3-STATE
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IS93C46D
AC WAVEFORMS FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING
tCS CS
DIN
1
1
1
An
An-1
A0
tSV DOUT
BUSY READY
tDF
tWP
Notes: To determine data bits An - A0, see Instruction Set for the appropriate device.
FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING
tCS
CS
DIN
1
0
0
1
0
tSV
tDF
READY
DOUT
BUSY
tWP
Note for Figures 8 and 9: After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.
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11
IS93C46D
ORDERING INFORMATION
Industrial Range: -40C to +85C Voltage Range 1.8V to 5.5V Order Part No. IS93C46D-2PI IS93C46D-2GRI Package 300-mil Plastic DIP SOIC JEDEC
ORDERING INFORMATION
Industrial Range: -40C to +85C, Lead-free Voltage Range 1.8V to 5.5V Order Part No. IS93C46D-2PLI IS93C46D-2DLI IS93C46D-2GRLI Package 300-mil Plastic DIP DFN SOIC JEDEC
ORDERING INFORMATION
Automotive Range: -40C to +125C, Lead-free Voltage Range 2.5V to 5.5V Order Part No. IS93C46D-3PLA3 IS93C46D-3GRLA3 Package 300-mil Plastic DIP SOIC JEDEC
12
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Rev. 00G 01/15/07
PACKAGING INFORMATION
150-mil Plastic SOP Package Code: G, GR
N
E
H
1 D
SEATING PLANE
A
A1 e B
L
C
Symbol Ref. Std. No. Leads A A1 B C D E H e L
150-mil Plastic SOP (G, GR) Min Max Min Max Inches mm 8 8 -- 0.068 -- 1.73 0.004 0.009 0.1 0.23 0.013 0.020 0.33 0.51 0.007 0.010 0.18 0.25 0.189 0.197 4.8 5 0.150 0.157 3.81 3.99 0.228 0.245 5.79 6.22 0.050 BSC 1.27 BSC 0.020 0.035 0.51 0.89
Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
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Rev. C 10/03/01
2
PACKAGING INFORMATION
Dual Flat No-Lead Package Code: D (8-pad)
A
D2
b (8X)
E2
E
tie bars(3)
Pad 1 ID
L (8X)
D A2 A3 A1
e (6X) 1.50 REF.
Pad 1 index area
DFN
MILLIMETERS Sym.
N0. Pad D E D2 E2 A A1 A2 A3 L e b 0.18 0.30 1.50 1.60 0.70 0.0 --
Min. Nom. Max.
8 2.00 BSC 3.00 BSC -- -- 0.75 0.02 -- 0.20 REF 0.40 0.50 BSC 0.25 0.30 0.50 1.75 1.90 0.80 0.05 0.75
Notes: 1. Refer to JEDEC Drawing MO-229. 2. This is the metallized terminal and is measured between 0.18 mm and 0.30 mm from the terminal tip. The terminal may have a straight end instead of rounded. 3. Package may have exposed tie bars, ending flush with package edge.
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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Rev. B 02/13/06
PACKAGING INFORMATION
300-mil Plastic DIP Package Code: N,P
N
E1
1 D SEATING PLANE B1
S
S
A
E
L FOR 32-PIN ONLY A1 e B B2
C eA
MILLIMETERS Sym.
N0. Leads A A1 B B1 B2 C D E E1 eA e L S
INCHES Min. Max.
Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should
Min.
8
Max.
be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
3.68 0.38 0.36 1.14 0.81 0.20 9.12 7.62
6.20 8.13 3.18 0.64
4.57 -- 0.56 1.52 1.17 0.33
9.53 8.26
6.60 9.65 -- 0.762
0.145 0.015 0.014 0.045 0.032 0.008 0.359 0.300
0.244 0.320 0.125 0.025
0.180 -- 0.022 0.060 0.046 0.013
0.375 0.325
0.260 0.380 -- 0.030
2.54 BSC
0.100 BSC
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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Rev. D 02/14/03
PACKAGING INFORMATION
300-mil Plastic DIP Package Code: N,P
MILLIMETERS Sym.
N0. Leads A A1 B B1 B2 C D E E1 eA e L S --
INCHES Min. Max. Sym.
N0. Leads
MILLIMETERS Min.
20
INCHES Min. Max.
Min.
16
Max.
Max.
3.68 0.25
4.57 --
0.46 BSC 1.52 BSC
-- 0.38
0.145 0.180 0.010 -- 0.018 BSC 0.060 BSC
-- -- 0.015
A A1 B B1 B2 C D E E1 eA e L S
3.68 0.38 0.36 1.14
--
4.57 -- 0.56 1.78 -- 0.36
0.145 0.015 0.014 0.045
--
0.180 -- 0.022 0.070 -- 0.014
0.13 18.92 7.44
6.22 8.13 3.05 0.38
19.18 8.13
6.48 9.65 3.56 0.89
0.005 0.745 0.293
0.245 0.320 0.120 0.015
0.755 0.320
0.255 0.380 0.140 0.035
0.20 25.91 7.49
6.01 -- 3.05 1.02
26.42 8.26
7.11 10.92
0.008 1.020 0.295
0.240 -- 0.120 0.040
1.040 0.325
0.280 0.430
2.54 BSC
0.100 BSC
2.54 BSC 3.81 1.52
0.100 BSC 0.150 0.060
MILLIMETERS Sym.
N0. Leads A A1 B B1 B2 C D E E1 eA e L S
INCHES Min. Max. Sym.
N0. Leads
MILLIMETERS Min.
32
INCHES Min. Max.
Min.
28
Max.
Max.
3.68 0.25 0.41
1.27
4.57 --
0.56
1.78
0.81 0.20 35.05 7.49
6.99 7.87 3.05 0.51
1.17
0.38
35.56 8.00
7.49 10.16 3.81 1.06
0.145 0.010 0.016 0.050 0.032 0.008 1.380 0.295
0.275 0.310 0.120 0.020
0.180 --
A A1 B B1 B2 C D E E1 eA e L S
0.022 0.070 0.046
0.015
3.56 0.38 0.38 1.02
--
4.57 -- 0.53 1.78 -- 0.38
0.140 0.015 0.015 0.040
--
0.180 -- 0.021 0.070 -- 0.015
1.400 0.315
0.295 0.400 0.150 0.042
0.13 40.51 7.75
7.24 8.38 3.05 1.65
40.77 8.26
7.22 9.40 3.81 2.16
0.005 1.595 0.305
0.285 0.33 0.120 0.065
1.605 0.325
0.292 0.370 0.150 0.085
2.54 BSC
0.100 BSC
2.54 BSC
0.100 BSC
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 02/14/03

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